--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;

entity proc_bitmanipulator is
	port (
		rst : in std_logic;
		clk : in std_logic;
		en : in std_logic;
		
		value_in : in PROC_REG_DATA_TYPE;
		value_out : out PROC_REG_DATA_TYPE;
		
		bit_index : in PROC_REG_BIT_INDEX_TYPE;
		bit_in : in std_logic;
		bit_eq : out std_logic
	);
end proc_bitmanipulator;

architecture Behavioral of proc_bitmanipulator is
	-- Signal of stored value
	signal reg_out_value : PROC_REG_DATA_TYPE := (others => '0');
	signal bit_eq_value : std_logic := '0';
begin

	value_out <= reg_out_value;
	bit_eq <= bit_eq_value;
	
	process(clk, rst)
		variable temp : PROC_REG_DATA_TYPE;
	begin
		if (rising_edge(clk)) then
			if (rst = '1') then
				reg_out_value <= (others => '0');
				bit_eq_value <= '0';
			elsif (en = '1') then
				temp := value_in;
				-- Compare Bit
				if (temp(conv_integer(bit_index)) = bit_in) then
					bit_eq_value <= '1';
				else
					bit_eq_value <= '0';
				end if;
				-- Modify Bit
				temp(conv_integer(bit_index)) := bit_in;
				reg_out_value <= temp;
			end if;
		end if;
	end process;

end Behavioral;

